发明名称 Viterbi pretraceback for partial cascade processing
摘要 This invention modifies Viterbi decoding to improve BER. Within the state metric unit cascade block, this invention forces the unused ACS units decision bits to a 0 for the top rail and a 1 for the bottom rail. This invention modifies the final maximum state index with the selected decision bits from the unused ACS units. This invention uses the modified final maximum state index as the initial conditions for the k-1 traceback shift register. This invention also uses the final maximum state index to mask the generated pretraceback decision bits generated from the last block of ACS units.
申请公布号 US7594162(B2) 申请公布日期 2009.09.22
申请号 US20060382822 申请日期 2006.05.11
申请人 TEXAS INSTRUMENTS INCORPORATED 发明人 WOLF TOD D.
分类号 H03M13/03 主分类号 H03M13/03
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