| 摘要 |
PROBLEM TO BE SOLVED: To achieve the high speed operation of a logic circuit by configuring the transistor of an operating node by one stage, and reducing a power supply voltage to be applied to the logic circuit. SOLUTION: This differential logic circuit is configured by connecting a series circuit of first and second FETs (M43, M44) connected in parallel and first load resistance (R42) and a series circuit of third and fourth FETs (M41, M42) connected in parallel and a second load resistance (R41) in parallel, and connecting it through an FET (M45) for current control to a DC power source, and configured to output the logical arithmetic result of a gate signal to be supplied to the first and second FET through the first load resistance. The FET to be serially connected across the power supply terminals of the DC power source is only one of the FET for current control and the first, second, third and fourth FETs, and when gate signals to be supplied to the first and second FET are both signals by which the first and second FET are driven OFF, at least either the third or fourth FET is driven ON. COPYRIGHT: (C)2009,JPO&INPIT
|
