发明名称 TEST WAFER UNIT AND TEST SYSTEM
摘要 Provided is a test wafer unit that tests a plurality of devices under test formed on a wafer under test, the test wafer unit comprising a plurality of test circuits that are formed on the same semiconductor wafer, where a plurality of types of the test circuits having different functions are provided for each device under test; and a selecting section that selects which type of test circuit is electrically connected to each pad of a device under test. Therefore, the test wafer unit can select the test circuit corresponding to testing content to be performed and connect this test circuit to the device under test to perform testing on a variety of devices under test or to perform a variety of tests on a device under test.
申请公布号 US2011133768(A1) 申请公布日期 2011.06.09
申请号 US20100947713 申请日期 2010.11.16
申请人 ADVANTEST CORPORATION 发明人 TOKUNAGA YASUO;KOMOTO YOSHIO
分类号 G01R31/00 主分类号 G01R31/00
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