| 摘要 |
<p>An integrated circuit comprising: a plurality of n-well and p-well regions (305, 306) arranged in alternating parallel rows across a plane of the integrated circuit; a deep n-well region (301) beneath the n-well and p-well regions (305, 306) and extending between first and second n-well region rows (305 1 , 305 2 ) either side of a third n-well region row (305 3 ); and a plurality of n-well region columns (307) connecting the first and second n-well region rows (305 1 , 305 2 ) and overlaying a portion of a boundary of the deep n-well region (301).</p> |
