发明名称 DESIGN INFORMATION GENERATION PROGRAM, DESIGN INFORMATION GENERATOR, AND DESIGN INFORMATION GENERATION METHOD
摘要 PROBLEM TO BE SOLVED: To efficiently manage information of a land without a user being conscious of layers, through which a via hole passes, of a printed wiring board, to facilitate designing the via hole. SOLUTION: Information on the shape and/or size of a land for surface layer and a land for inner layer provided around the via hole is stored. When generating design information of the via hole passing through a plurality of inner layers of the printed wiring board, the design information is generated by applying the stored information of the shape and/or size of the land for inner layer to the respective inner layers which the via hole passes through. COPYRIGHT: (C)2011,JPO&INPIT
申请公布号 JP2011076614(A) 申请公布日期 2011.04.14
申请号 JP20100246888 申请日期 2010.11.02
申请人 FUJITSU LTD 发明人 KAWAMICHI TAKETSUGU;NAKAMURA HIROSHI;KONNO EIICHI
分类号 G06F17/50;H05K3/00 主分类号 G06F17/50
代理机构 代理人
主权项
地址