发明名称 Single-wire asynchronous serial interface
摘要 The present invention discloses a single-wire asynchronous serial interface, and a method for transmitting commands and data through one transmission wire, wherein the transmission wire is capable of transmitting signals of three level states. The disclosed interface comprises a signal level extraction circuit receiving signals transmitted through the wire and outputting logic or functional bits according to the received signals; a clock extraction circuit generating clock signals according to the functional bits, and a memory circuit controlled by the clock signals and storing the logic bits. The disclosed method comprises: using two of the level states to represent logic 0 and logic 1, and the third of the states as a functional bit; and determining whether a group of signals is a command or data by the existence of a functional bit within the group.
申请公布号 US8369443(B2) 申请公布日期 2013.02.05
申请号 US201113175906 申请日期 2011.07.04
申请人 RICHTEK TECHNOLOGY CORPORATION R.O.C.;CHEN ISAAC Y. 发明人 CHEN ISAAC Y.
分类号 H04L25/49 主分类号 H04L25/49
代理机构 代理人
主权项
地址