发明名称 |
Low cost and high speed architecture of montgomery multiplier |
摘要 |
A system to perform Montgomery multiplication includes a first multiplier array configured to multiply w bits of an operand X by W bits of an operand Y, where w and W are integers and w is less than W. A second multiplier array is configured to multiply w bits of an operand Q by W bits of a modulo M. An adder array is configured to add outputs of the first and second multiplier arrays to generate a sum. A partial sum array is configured to store a left portion of the sum. A memory is configured to store a right portion of the sum. Q computation logic includes a lookup table and a half-multiplier that compute W bits of the operand Q sequentially in 2 · W w cycles or W w cycles. The W bits of the operand Q are stored in the fourth buffer for use by subsequent W×W operations.
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申请公布号 |
US8527570(B1) |
申请公布日期 |
2013.09.03 |
申请号 |
US20100855340 |
申请日期 |
2010.08.12 |
申请人 |
SHU CHANG;TANG HENG;LEE SEAN;MARVELL INTERNATIONAL LTD. |
发明人 |
SHU CHANG;TANG HENG;LEE SEAN |
分类号 |
G06F7/38 |
主分类号 |
G06F7/38 |
代理机构 |
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