发明名称 |
FORMING EMBEDDED SOURCE AND DRAIN REGIONS TO PREVENT BOTTOM LEAKAGE IN A DIELECTRICALLY ISOLATED FIN FIELD EFFECT TRANSISTOR (FINFET) DEVICE |
摘要 |
Approaches for isolating source and drain regions in an integrated circuit (IC) device (e.g., a fin field effect transistor (finFET)) are provided. Specifically, the FinFET device comprises a gate structure formed over a finned substrate; an isolation oxide beneath an active fin channel of the gate structure; an embedded source and a drain (S/D) formed adjacent the gate structure and the isolation oxide; and an epitaxial (epi) bottom region of the embedded S/D, the epi bottom region counter doped to a polarity of the embedded S/D. The device further includes a set of implanted regions implanted beneath the epi bottom region, wherein the set of implanted regions may be doped and the epi bottom region undoped. In one approach, the embedded S/D comprises P++ doped Silicon Germanium (SiGe) for a p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET) and N++ Silicon Nitride (SiN) for a n-channel metal-oxide-semiconductor field-effect transistor (NMOSFET). |
申请公布号 |
US2015028348(A1) |
申请公布日期 |
2015.01.29 |
申请号 |
US201313948374 |
申请日期 |
2013.07.23 |
申请人 |
Globalfoundries Inc. |
发明人 |
Jacob Ajey Poovannummoottil;Akarvardar Murat K. |
分类号 |
H01L29/78;H01L29/66 |
主分类号 |
H01L29/78 |
代理机构 |
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代理人 |
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主权项 |
1. A device comprising:
a gate structure formed over a finned substrate; an embedded source and a drain (S/D) adjacent the gate structure; and an epitaxial (epi) bottom region of the embedded S/D, the epi bottom region counter doped to a polarity of the embedded S/D. |
地址 |
Grand Cayman KY US |