| 摘要 |
PROBLEM TO BE SOLVED: To provide a low power signaling system.SOLUTION: In a memory system 100 including a clock stop low power mode, a memory device 103 includes an open loop clock distribution circuit and a transmission circuit, enabling high speed transmission of an information transportation symbol that does not accompany a source synchronous timing reference by cooperation. The open loop clock distribution circuit generates a transmission clock signal in response to a system clock link 108, and the transmission circuit outputs a symbol sequence to a data link 106 in response to transition of the transmission clock signal. Each symbol is effective across a symbol time at an output of the transmission circuit. A phase offset between the transmission clock signal and an external supply clock signal is allowed to drift at least only the symbol time. |
