Computer Processor Employing Efficient Bypass Network For Result Operand Routing

摘要

A computer processor is provided with a plurality of functional units that performs operations specified by the at least one instruction over the multiple machine cycles, wherein the operations produce result operands. The processor also includes circuitry that generates result tags dynamically according to the number of operations that produce result operands in a given machine cycle. A bypass network is configured to provide data paths for transfer of operand data between the plurality of functional units according to the result tags.

主权项

1. A computer processor comprising:
a plurality of functional units that performs operations specified by the at least one instruction over the multiple machine cycles, wherein the operations produce result operands; and circuitry that generates result tags dynamically according to the number of operations that produce result operands in a given machine cycle; and a bypass network that provides data paths for transfer of result operands between the plurality of functional units according to said result tags.