Training for command/address/control/clock delays under uncertain initial conditions and for mapping swizzled data to command/address signals

摘要

Data pin mapping and delay training techniques. Valid values are detected on a command/address (CA) bus at a memory device. A first part of the pattern (high phase) is transmitted via a first subset of data pins on the memory device in response to detecting values on the CA bus; a second part of the pattern (low phase) is transmitted via a second subset of data pins on the memory device in response to detecting values on the CA bus. Signals are sampled at the memory controller from the data pins while the CA pattern is being transmitted to obtain a first memory device's sample (high phase) and the second memory device's sample (low phase) by analyzing the first and the second subset of sampled data pins. The analysis combined with the knowledge of the transmitted pattern on the CA bus leads to finding the unknown data pins mapping. Varying the transmitted CA patterns and the resulting feedbacks sampled on memory controller data signals allows CA/CTRL/CLK signals delay training with and without priory data pins mapping knowledge.

主权项

1. A method comprising:
detecting valid values on a command/address (CA) bus at a memory device; transmitting, with a memory controller, a first pattern on the CA bus resulting in DRAM transmitting a first set of values on the Data pins producing a unique sum of ‘1’-s per byte sampling signals from the data pins after the first pattern is being transmitted to obtain a first sample; transmitting, with the memory controller, a second pattern on the CA bus resulting in DRAM transmitting a second set of values on the Data pins producing a unique sum of ‘1’-s per byte sampling signals from the data pins after the second pattern is being transmitted to obtain a second sample; using the first sample and the second sample to generate a data pin mapping.