| 发明名称 |
CONSTRAINING PREFETCH REQUESTS TO A PROCESSOR SOCKET |
| 摘要 |
In an embodiment, a processor includes at least one core having one or more execution units, a first cache memory and a first cache control logic. The first cache control logic may be configured to generate a first prefetch request to prefetch first data, where this request is to be aborted if the first data is not present in a second cache memory coupled to the first cache memory. Other embodiments are described and claimed. |
| 申请公布号 |
US2015149714(A1) |
申请公布日期 |
2015.05.28 |
| 申请号 |
US201314090056 |
申请日期 |
2013.11.26 |
| 申请人 |
Pugsley Seth H.;Scott Robert L.;Chishti Zeshan A.;Chuang Peng-Fei;Ban Khun;Wilkerson Christopher B.;Lu Shih-Lien L.;Chow Kingsum |
发明人 |
Pugsley Seth H.;Scott Robert L.;Chishti Zeshan A.;Chuang Peng-Fei;Ban Khun;Wilkerson Christopher B.;Lu Shih-Lien L.;Chow Kingsum |
| 分类号 |
G06F12/08;G11C11/406 |
主分类号 |
G06F12/08 |
| 代理机构 |
|
代理人 |
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| 主权项 |
1. A processor comprising:
at least one core including one or more execution units, a first cache memory and a first cache control logic, wherein the first cache control logic is to generate a first prefetch request to prefetch first data, wherein the first prefetch request is to be aborted if the first data is not present in a second cache memory coupled to the first cache memory. |
| 地址 |
Salt Lake City UT US |
