发明名称 Method of manufacturing semiconductor device
摘要 To provide a semiconductor device having improved reliability at an improved production yield.;After forming an insulating film on the main surface of a semiconductor substrate as an oxide film, form a silicon nitride film on the insulating film. Then, form an element isolating trench by plasma dry etching, form an insulating film made of silicon oxide so as to fill the trench by using HDP-CVD, and remove the insulating film outside the trench by CMP, while leaving the insulating film in the trench. Then, remove the silicon nitride film, followed by removal of the insulating film by wet etching to expose the semiconductor substrate. At this time, the insulating film is wet etched while applying light of 140 lux or greater to the main surface of the semiconductor substrate.
申请公布号 US9142443(B2) 申请公布日期 2015.09.22
申请号 US201213540547 申请日期 2012.07.02
申请人 Renesas Electronics Corporation 发明人 Hasegawa Kazuhiko
分类号 H01L21/762;H01L21/311;H01L21/67;H01L21/8234 主分类号 H01L21/762
代理机构 Miles & Stockbridge P.C. 代理人 Miles & Stockbridge P.C.
主权项 1. A method of manufacturing a semiconductor device, comprising the steps of: (a) preparing a semiconductor substrate; (b) forming a first insulating film over the main surface of the semiconductor substrate; (c) forming an element isolating trench in the first insulating film and the semiconductor substrate by plasma dry etching of the first insulating film and the semiconductor substrate; (d) forming a second insulating film over the main surface of the semiconductor substrate so as to fill the trench; (e) removing the second insulating film outside the trench by CMP, while leaving the second insulating film in the trench; (f) after step (e), removing the first insulating film by wet etching to expose the semiconductor substrate, the first insulating film being wet etched while applying light of 140 lux or greater to the first insulating film; (g) after step (f), implanting a dopant into the semiconductor substrate to form a well; and (h) after the step (g), forming a gate insulating film of a MISFET over the well.
地址 Tokyo JP