发明名称 マルチバンクLLRバッファを含むデインターリーブ機構
摘要 <p>A de-interleaver generates a plurality of De-interleaved Reorder Physical (DRP) addresses to simultaneously write a corresponding plurality of LLR values into a multi-banked memory such that not more than one LLR value is written into each bank of the multi-banked memory at a time. A sequence of such parallel writes results in the LLR values of a transmission of a sub-packet being stored in the memory. Address translation performed during generation of the DRP addresses causes the LLR values to be stored within the banks such that a decoder can read LLR values out of the memory in a de-interleaved sequence. Each memory location of a bank is a word-location for storing multiple related LLR values, where one LLR value is stored along with its parity values. The ability to simultaneously write to multiple LLR values is used to clear locations in a fast and efficient manner.</p>
申请公布号 JP5801353(B2) 申请公布日期 2015.10.28
申请号 JP20130147120 申请日期 2013.07.12
申请人 クゥアルコム・インコーポレイテッドQUALCOMM INCORPORATED 发明人 アリ・ロスタンピシェー;ラグー・エヌ.・チャッラ;イウェン・ヤオ;デイブ・ジェイ.・サントス;ムリナル・エム.・ネイス
分类号 H03M13/27;H04L1/00 主分类号 H03M13/27
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