| 摘要 |
<p>The circuit for comparing phase differences betweenwrite and read clocks of a buffer to generate a error signal when the phase difference is more than a predetermined value, comprises a clock-phase comparing means (EN1,AN1) for comparing the phase differences and forming a path of count clock upon arror generation, a means (FD1,AN2) for receiving a carry output signal fromthe buffer to generate an error searching signal for error counting, a counting means (CNT1,AN3,NR1) for counting the number of count clock to generate a warning signal if the number of count clock in more than a predetermined value, and a means (FD2) for applying the warning signal to a control unit of the async. multiplexing system.</p> |
