| 摘要 |
<p>PURPOSE:To eliminate the need for the delay processing of a clock, etc., and to prevent a malfunction due to skew time by using an FF for controlling separately timing storing input data and the timing outputting stored data. CONSTITUTION:FF cells 10, 20 in an LSI 11 control separately the timing for storing the input data and the timing for outputting the stored data by using inputted clock signals CLK1-P, CLK2-P. Then, each of the FF 10 of a preceding stage and the FF 20 of a poststage is provided with an input side FF and an output side FF respectively and the input side FF determines the timing for storing the input data and the output side FF determines the timing for outputting the stored data. Namely, by inverting the clocks CLK1-P, CLK2-P by inverters 13, 23, the data DT10-P, DT20-P are outputted at the timing delayed by one period. Then, the malfunction can be prevented by making the pulse width of the clock larger than clock skew.</p> |
