| 摘要 |
An image processing apparatus which can reduce the power consumption by a large extent, wherein a predetermined shape to be displayed on a display is expressed by a composite of unit graphics by performing operations on a plurality of pixels simultaneously and by performing processing on valid results of operations for pixels positioned inside a unit graphic being processed. Clock enablers in operation sub-blocks judge the validity of the corresponding val data. Only operation sub-blocks receiving the corresponding val data indicating validity perform operations. Other operation sub-blocks do not perform operations. The operation blocks perform pipeline processing.
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