Dynamic per-decoder control of log likelihood ratio and decoding parameters

摘要

An apparatus includes one or more error-correction decoders, a buffer, at least one direct memory access (DMA) engine, and at least one processor. The buffer may be configured to store data to be decoded by the one or more error-correction decoders. The at least one DMA engine may couple the buffer and the one or more error-correction decoders. The at least one processor may be enabled to send messages to the at least one DMA engine. The messages may be configured to deliver DMA control information and corresponding datapath control information. Data may be read from the buffer based upon the DMA control information and delivered to the one or more error-correction decoders along with the corresponding datapath control information. The one or more error-correction decoders may be enabled to decode the data read from the buffer according to the corresponding datapath control information.

主权项

1. An apparatus comprising:
one or more error-correction decoders; a buffer configured to store data to be decoded by the one or more error-correction decoders; at least one direct memory access (DMA) engine coupling the buffer and the one or more error-correction decoders; and at least one processor enabled to send messages to the at least one DMA engine, wherein the messages are configured to deliver DMA control information and corresponding datapath control information, the data is read from the buffer based upon the DMA control information and delivered to the one or more error-correction decoders along with the corresponding datapath control information, and the one or more error-correction decoders are enabled to decode the data read from the buffer according to the corresponding datapath control information.