Liquid crystal display device and electronic device

摘要

To provide a circuit used for a shift register or the like. The basic configuration includes first to fourth transistors and four wirings. The power supply potential VDD is supplied to the first wiring and the power supply potential VSS is supplied to the second wiring. A binary digital signal is supplied to each of the third wiring and the fourth wiring. An H level of the digital signal is equal to the power supply potential VDD, and an L level of the digital signal is equal to the power supply potential VSS. There are four combinations of the potentials of the third wiring and the fourth wiring. Each of the first transistor to the fourth transistor can be turned off by any combination of the potentials. That is, since there is no transistor that is constantly on, deterioration of the characteristics of the transistors can be suppressed.

主权项

1. A semiconductor device comprising:
a first transistor, a second transistor, a third transistor and a fourth transistor; wherein one of a source and a drain of the first transistor is electrically connected to a first wiring, wherein a gate of the first transistor is electrically connected to the first wiring, wherein one of a source and a drain of the second transistor is electrically connected to a second wiring, wherein the other of the source and the drain of the second transistor is electrically connected to the other of the source and the drain of the first transistor, wherein one of a source and a drain of the third transistor is electrically connected to the second wiring, wherein the other of the source and the drain of the third transistor is electrically connected to the other of the source and the drain of the first transistor, wherein a gate of the third transistor is electrically connected to a third wiring, wherein one of a source and a drain of the fourth transistor is electrically connected to the second wiring, wherein a gate of the fourth transistor is electrically connected to the other of the source and the drain of the first transistor, and wherein at least one of a ratio of a channel width to a channel length of the second transistor and a ratio of a channel width to a channel length of the third transistor is higher than a ratio of a channel width to a channel length of the first transistor.