REPLACEMENT METAL GATE INCLUDING DIELECTRIC GATE MATERIAL

摘要

A method of fabricating a semiconductor device includes forming at least one semiconductor fin on a semiconductor substrate. A plurality of gate formation layers is formed on an etch stop layer disposed on the fin. The plurality of gate formation layers include a dummy gate layer formed from a dielectric material. The plurality of gate formation layers is patterned to form a plurality of dummy gate elements on the etch stop layer. Each dummy gate element is formed from the dielectric material. A spacer layer formed on the dummy gate elements is etched to form a spacer on each sidewall of dummy gate elements. A portion of the etch stop layer located between each dummy gate element is etched to expose a portion the semiconductor fin. A semiconductor material is epitaxially grown from the exposed portion of the semiconductor fin to form source/drain regions.

主权项

1. A method of fabricating a semiconductor device, the method comprising:
forming at least one semiconductor fin on a semiconductor substrate; forming an etch stop layer on an upper surface of the at least one semiconductor fin; forming a plurality of dummy gate elements on the etch stop layer, each dummy gate element formed from a dielectric material and having a hardmask gate cap formed on an upper surface of the semiconductor fin; depositing a high-dielectric constant layer that conforms to an outer surface of each dummy gate element and depositing a spacer layer on the high-dielectric constant layer; performing a first etching process that etches the spacer layer to form a spacer on each sidewall of dummy gate elements and exposes an upper portion of the high-dielectric constant layer; performing a second etching process different from the first etching process that selectively etches the upper portion of the high-dielectric constant layer to expose each hardmask gate cap; removing the hardmask gate caps and the dummy gate elements to form a trench between a respective pair of spacers; and performing a third etching process after removing the dummy gates elements to remove a portion of the high-dielectric constant material from the sidewalls of the spacers such that a remaining portion of the high-dielectric constant material is interposed between the spacers and the etch stop layer.