Self-aligned fine pitch permanent on-chip interconnect structures and method of fabrication

摘要

An interconnect structure and methods for making the same include sidewall portions of an interlevel dielectric layer. The sidewall portions have a width less than a minimum feature size for a given lithographic technology and the width is formed by a thickness of the interlevel dielectric layer when conformally formed on vertical surfaces of a mandrel. The sidewall portions form spaced-apart openings. Conductive structures fill the spaced-apart openings and are separated by the sidewall portions to form single damascene structures.

主权项

1. An interconnect structure for an integrated circuit device, comprising:
a plurality of sidewall portions of an interlevel dielectric layer, the sidewall portions having a width less than a minimum feature size for a given lithographic technology and the width being formed by a thickness of the interlevel dielectric layer when conformally formed on vertical surfaces of a mandrel, the sidewall portions forming spaced-apart openings; and conductive structures filling the spaced-apart openings and separated by the sidewall portions to form single damascene structures, wherein the conductive structures are the interconnects to semiconductor devices in a substrate that the interlevel dielectric layer is present on, wherein each interface between the interconnects and the plurality of sidewall portions is planar.