发明名称 |
Reduced PTH pad for enabling core routing and substrate layer count reduction |
摘要 |
Embodiments are directed to semiconductor packaging having reduced sized plated through hole (PTH) pads by eliminating the margin of the pad-to-PTH alignment and enabling finer traces on the core of the substrate. |
申请公布号 |
US9210809(B2) |
申请公布日期 |
2015.12.08 |
申请号 |
US201314097932 |
申请日期 |
2013.12.05 |
申请人 |
Intel Corporation |
发明人 |
Mallik Debendra;Roy Mihir |
分类号 |
H01L23/52;H01L23/48;H05K1/11;H01L21/48;H01L23/498 |
主分类号 |
H01L23/52 |
代理机构 |
Winkle, PLLC |
代理人 |
Winkle, PLLC |
主权项 |
1. An apparatus, comprising:
a substrate core comprising a resin extending throughout the substrate core, and glass fibers and filler material within the resin; at least one resin rich outer area within the substrate core; a plurality of plated through holes (PTHs) extending through the substrate core to provide vertical electrical paths through the core, the PTHs having a diameter of approximately 100 μm at a top and bottom side of the core; and a plurality of trace lines between the PTHs having line spacing (L/S) of approximately 20 μm/20 μm. |
地址 |
Santa Clara CA US |