Glitchless clock switching that handles stopped clocks

摘要

An integrated circuit receives a first and second clock signal and a select signal that selects one of the clock signals. A glitchless switching circuit supplies an output clock signal according to which of the first and second clocks is selected by the select signal. A reset circuit coupled to the glitchless switching circuit responds to a direction of a transition of the select signal and generates a first reset signal in response to a first direction of the transition and generates a second reset signal in response to a second direction of the transition. The reset pulses are supplied respectively to first and second paths in the glitchless switching circuit to reset the state machine formed by the first and second paths in the event one of the input clocks is absent.

主权项

1. A method comprising:
generating an output clock signal using one of a first clock signal and a second clock signal; receiving a transition of a select signal indicating to switch from generating the output clock signal using the one of the first clock signal and the second clock signal to generating the output clock signal using another of the first clock signal and the second clock signal; generating a first reset signal responsive to a direction of the transition of the select signal being in a first direction; generating a second reset signal responsive to the direction of the transition of the select signal being in a second direction; supplying the first reset signal to reset a first circuit forming a first path used by the first clock signal if the direction of the transition is in the first direction; and supplying the second reset signal to reset a second circuit forming a second path used by the second clock signal if the direction of the transition is in the second direction.