Reset of processing core in multi-core processing system

摘要

This disclosure is directed to performing a controlled reset of one or more cores while maintaining operation of at least one other core in a multi-core processor. An initialization core may include reset logic that may detect a problematic core or core that is unresponsive or otherwise not operating properly. The initialization core may generate a packet that enables communication with the problematic core. The initialization core may send a reset packet to the problematic core to instruct the problematic core to perform a reset.

主权项

1. A processor comprising:
a plurality of processing cores; an interconnect coupled to the plurality of processing cores; and a first logic to detect a non-responding processing core from the plurality of processing cores and to transmit reset information to the non-responding processing core on the interconnect, wherein the reset information is to be formatted into a packet, wherein the reset information includes a reset operation to power-off the non-responsive processing core and unreset information to power-on the non-responsive processing core.