CIRCUIT AND METHOD FOR CLOCK AND DATA RECOVERY

摘要

A clock and data recovery circuit to which a phase detector and a charge pump are applied, based on sub-sampling is disclosed. The clock and data recovery circuit according to the present invention comprises: a voltage control oscillator which generates multi-phase clock signals by changing the frequency of a clock signal on the basis of input control voltage; a phase detector which detects the phase difference from input data by sampling first multi-phase clock signals as a part of the multi-phase clock signals in response to the input data; a charge pump which generates control current on the basis of the phase difference detected by the phase detector; a loop filter which generates control voltage to be input to the voltage control oscillator by integrating the control current output from the charge pump; and a deserializer which restores the input data by sampling second multi-phase clock signals which are other phase clock signals except for the first multi-phase clock signals of the multi-phase clock signals, with the input data, and deserializes and samples the second multi-phase clock signals.