| 摘要 |
PROBLEM TO BE SOLVED: To provide a variable delay circuit that adjusts a delay amount to be applied to an input signal with resolution shorter than the oscillation period of a clock signal.SOLUTION: A variable delay circuit 1 has an oscillation circuit part 10 for generating clock signals CLK1 to CLKn of n phases which have the same oscillation period and are displaced in phase by every 1/n of the oscillation period (n represents a natural number of 2 or more), and a delay circuit part 20 for delaying an input signal IN by using the clock signals CLK1 to CLKn to generate an output signal OUT. The delay circuit part 20 adjusts the delay amount on the basis of a delay amount setting signal DSET by using the phase difference of the clock signals CLK1 to CLKn as the minimum variable unit. |
