发明名称 ISOLATOR/CIRCULATOR WITH IMPROVED LOSS AND BANDWITH
摘要 An isolator/circulator circuit for use in any kind of electronic system wherein reflected signal insertion loss is eliminated or minimized while bandwidth of the system is generally unlimited and limited only by the bandwidth of the amplifiers PA1 and PA2 and by the bandwidth of the divider/combiner X2 and X4, one (1) octave as minimum and several as maximum. The circuit allows this technique to be used in low frequency applications below MHz range where circulator/isolator sizes/cost become prohibitive and physically impossible to fabricate.
申请公布号 US2015349395(A1) 申请公布日期 2015.12.03
申请号 US201514725038 申请日期 2015.05.29
申请人 Starri Ernesto G.F. 发明人 Starri Ernesto G.F.
分类号 H01P1/32;H03F3/189;H03F3/20;H03F3/68 主分类号 H01P1/32
代理机构 代理人
主权项 1. An isolator/circulator circuit, comprising: an analog input signal receiving port, configured for receiving an analog input signal; a divider element, electrically coupled to said analog input signal receiving port and configured for providing first and second analog divider output signals in response to said analog input signal received on said analog input signal receiving port, wherein said first and second analog divider output signals each have a phase that is shifted 90 degrees in phase relative to one another; a first phase shifter, said first phase shifter X3 electrically coupled to said second analog divider output of said divider element and to a reflected output signal received from a reflected output signal port, said first phase shifter configured for varying a phase of said second analog divider output of said divider element and said reflected output signal, and for providing a directly proportional phase variation signal to a second amplifier PA2; a delay element X1, electrically coupled to said first analog divider output of said divider element, and configured for providing a delay to said first analog divider output signal, said delay comprising of a predetermined period of time corresponding to a period of time delay introduced by said first phase shifter to said second analog divider output signal of said divider element when said first phase shifter phase shift is ZERO, and for providing an output signal to a first amplifier; and a combiner, electrically coupled to said outputs of each of said first and said second amplifiers, and configured for providing first and second combiner outputs, wherein said first and second combiner outputs (17, 19) are shifted 180 degrees in phase relative to one another, wherein said first combiner output is provided to an RF output port and wherein said second combiner output is provided to a load element.
地址 Riverside CA US