| 主权项 |
1. A clock and data recovery (CDR) circuit comprising:
a first data delaying cell that receives a received data signal, delays the received data signal and outputs a resulting first data signal; a second data delaying cell that receives the first data signal, delays the first data signal and outputs a resulting second data signal; a first oscillation delaying cell that receives an oscillation clock signal, delays the oscillation clock signal and outputs a resulting first clock signal, the first oscillation delaying cell setting a logic of the first clock signal to be the same as a logic of the oscillation clock signal in a case where a logic of the received data signal is a first logic and setting the logic of the first clock signal to be an inversion of the logic of the oscillation clock signal in a case where the logic of the received data signal is a second logic, which is an inversion of the first logic; a second oscillation delaying cell that receives the first clock signal, delays the first clock signal and outputs a resulting second clock signal, the second oscillation delaying cell setting a logic of the second clock signal to be the same as the logic of the first clock signal in a case where a logic of the first data signal is the second logic and setting the logic of the second clock signal to be an inversion of the logic of the first clock signal in a case where the logic of the first data signal is the first logic; a third oscillation delaying cell that receives the second clock signal, delays the second clock signal and outputs a resulting third clock signal; and a fourth oscillation delaying cell that receives the third clock signal, delays and inverts a logic of the third clock signal, and outputs a resulting fourth clock signal as the oscillation clock signal, the second data signal is output at a data output terminal as a recovery data signal, and the oscillation clock signal is output at a clock output terminal as a recovery clock signal. |
