发明名称 |
Clock adjustment circuit and digital to analog converting device |
摘要 |
A clock adjustment circuit and a digital to analog converting device are provided. The clock adjustment circuit includes a selection circuit and a frequency decreasing circuit. The selection circuit is configured to generate a first selection signal in response to a frequency of an output clock signal. The frequency decreasing circuit is coupled to the selection circuit, and configured to generate the output clock signal by reducing a frequency of an input clock signal by a first ratio in response to a first level of the first selection signal, and configured to generate the output clock signal by reducing the frequency of the input clock signal by a second ratio in response to a second level of the first selection signal, wherein the first ratio is different from the second ratio. Accordingly, complexity of a circuit is reduced. |
申请公布号 |
US9203384(B2) |
申请公布日期 |
2015.12.01 |
申请号 |
US201414277004 |
申请日期 |
2014.05.13 |
申请人 |
Phisontech Electronics (Malaysia) Sdn Bhd. |
发明人 |
Thian Nyuk-How;Hsu Chih-Jen |
分类号 |
H03M1/66;H03K5/04;H03K5/00 |
主分类号 |
H03M1/66 |
代理机构 |
Jianq Chyun IP Office |
代理人 |
Jianq Chyun IP Office |
主权项 |
1. A clock adjustment circuit for generating an output clock signal by tracking an input clock signal, the clock adjustment circuit comprising:
a selection circuit, configured to generate a first selection signal in response to a frequency of the output clock signal; and a frequency decreasing circuit, coupled to the selection circuit, and configured to generate the output clock signal by reducing a frequency of the input clock signal by a first ratio in response to a first level of the first selection signal, and configured to generate the output clock signal by reducing the frequency of the input clock signal by a second ratio in response to a second level of the first selection signal, wherein the first ratio is different from the second ratio. |
地址 |
Penang MY |