发明名称 |
INFORMATION PROCESSING APPARATUS AND BUS CONTROL METHOD |
摘要 |
An information processing apparatus includes: a plurality of memories; a plurality of buses each connected to each of the memories; an input/output device configured to make access to the plurality of memories; a processing unit configured to alter a mapping of a logical address and a physical address of a memory area used by the input/output device; and a switch configured to transfer access from the input/output device to any one of the plurality of buses based on the mapping, whereby the performance deterioration due to bus conflict is suppressed. |
申请公布号 |
US2015339246(A1) |
申请公布日期 |
2015.11.26 |
申请号 |
US201514656804 |
申请日期 |
2015.03.13 |
申请人 |
FUJITSU LIMITED |
发明人 |
SAKURAI Hiroshi |
分类号 |
G06F13/28;G06F13/40 |
主分类号 |
G06F13/28 |
代理机构 |
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代理人 |
|
主权项 |
1. An information processing apparatus comprising:
a plurality of memories; a plurality of buses each connected to each of the memories; an input/output device configured to make access to the plurality of memories; a processing unit configured to alter a mapping of a logical address and a physical address of a memory area used by the input/output device; and a switch configured to transfer access from the input/output device to any one of the plurality of buses based on the mapping. |
地址 |
Kawasaki-shi JP |