| 摘要 |
The invention relates to a processor comprising: several processing units (PU1-PU4) for a parallel processing of several elementary instructions (Pj) each comprising one or more syllables (Pj[1], Pj[2]) each having a rank in the elementary instruction, and an input circuit (INC, INC') configured for receiving a packet of instructions (IW) comprising several elementary instructions, and for transmitting to the processing units all the syllables of first rank (Pj[1]) of the elementary instructions of the packet of instructions before syllables of second rank (Pj[2]) of the elementary instructions of the packet of instructions, the syllables of the same rank being ordered mutually as a function of the processing unit for which each syllable is intended. |
