PROVIDING MEMORY BANDWIDTH COMPRESSION USING COMPRESSED MEMORY CONTROLLERS (CMCs) IN A CENTRAL PROCESSING UNIT (CPU)-BASED SYSTEM

摘要

Providing memory bandwidth compression using compressed memory controllers (CMCs) in a central processing unit (CPU)-based system is disclosed. In this regard, in some aspects, a CMC is configured to receive a memory read request to a physical address in a system memory, and read a compression indicator (CI) for the physical address from a master directory and/or from error correcting code (ECC) bits of the physical address. Based on the CI, the CMC determines a number of memory blocks to be read for the memory read request, and reads the determined number of memory blocks. In some aspects, a CMC is configured to receive a memory write request to a physical address in the system memory, and generate a CI for write data based on a compression pattern of the write data. The CMC updates the master directory and/or the ECC bits of the physical address with the generated CI.

主权项

1. A compressed memory controller, comprising a memory interface configured to access a system memory via a system bus;
the compressed memory controller configured to:
receive a memory read request comprising a physical address of a memory block to be accessed within a memory line in the system memory;read a master directory memory block containing a compression indicator (CI) corresponding to the physical address from a master directory in the system memory;determine, based on the CI, a number of memory blocks within the memory line in the system memory to read for the memory read request; andread the determined number of memory blocks within the memory line in the system memory beginning at the physical address.