VIRTUAL CELL MODEL GEOMETRY COMPRESSION

摘要

Semiconductor designs are large and complex, typically consisting of numerous circuits called cells. To handle complexity, hierarchical structures are imposed on the semiconductor design to help accomplish analysis, simulation, verification, and so on. The hierarchical structures define architecture, behavior, function, structure, etc. of the semiconductor design. Virtual cells are constructed to compress cell geometries and ease the various design tasks. A cell and multiple instances of the cell are identified within the semiconductor design and the virtual hierarchical levels describing the design. Virtual hierarchical layer (VHL) data based on the cell is loaded. A virtual cell model representative of the cell is obtained. Interactions between cell data and VHL data are determined, and relevant portions of shapes are selected. Data within the virtual cell model is reduced based on the determined interactions.

主权项

1. A computer-implemented method for design analysis comprising:
identifying a cell and multiple instances of the cell from a semiconductor design including a plurality of cells and a plurality of virtual hierarchical levels; loading virtual hierarchical layer (VHL) data based on the cell; obtaining a virtual cell model, representative of the cell; determining interactions, between data within the cell and the VHL data, and selecting relevant portions of shapes based on the determining; and reducing an amount of data within the virtual cell model based on the interactions which were determined.