Magnetoresistive memory device with reduced leakage and high speed operation in an SoC

摘要

According to one embodiment, a magnetoresistive memory device includes first and second bit lines, a memory cell, a power supply line, first and second transistors, and third and fourth transistors. The memory cell has first and second magnetoresistive elements and is connected between the first and second bit lines. The power supply line is connected between the first and second magnetoresistive elements. The first and second transistors have current paths inserted in the first and second bit lines, respectively, and have gate electrodes connected, respectively to the second and first bit lines provided on a side opposite to the memory cell. The third and fourth transistors are inserted in the first and second bit lines. Gate electrodes of the third and fourth transistors are cross-coupled, and the third and fourth transistors are controlled by current from the memory cell.

主权项

1. A magnetoresistive memory device comprising:
first and second bit lines; a memory cell comprising a first magnetoresistive element and a first transistor serially connected between the first bit line and a power supply line, and a second magnetoresistive element and a second transistor serially connected between the second bit line and the power supply line, gate electrodes of the first and second transistors being connected to a word line; third and fourth transistors having current paths inserted in the first and second bit lines, gate electrodes of the third and fourth transistors being connected, respectively, to the second and first bit lines provided on a side opposite to the memory cell; and fifth and sixth transistors connected to the first and second bit lines of the third and fourth transistors on the side opposite to the memory cell, the fifth and sixth transistors being configured to be turned on in response to a signal indicating that data is to be read from the memory cell.