发明名称 ARITHMETIC PROCESSOR AND CONTROL METHOD FOR ARITHMETIC PROCESSOR
摘要 PROBLEM TO BE SOLVED: To suppress the matching of addresses from being erroneously detected, and to suppress an instruction from being aborted without increasing a circuit scale.SOLUTION: A storage information storage part is configured to store first partial destination address information as a part of a destination address included in a store instruction while data are stored in a buffer part and hit information output by a control part on the basis of the store instruction. The determination part is configured to, when a part of the first partial source address information as a part of a source address included in a load instruction following the store instruction is overlapped with the first partial destination address information, determine the continuation of the load instruction on the basis of the hit information to be output by the control part in accordance with the source address included in the load instruction and the hit information stored in the store information storage part.
申请公布号 JP2015210577(A) 申请公布日期 2015.11.24
申请号 JP20140090273 申请日期 2014.04.24
申请人 FUJITSU LTD 发明人 KANAI YUKI;TAKAGI NORIKO
分类号 G06F12/08;G06F9/38 主分类号 G06F12/08
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