Low-temperature wafer level processing for MEMS devices

摘要

It would be beneficial to integrate MEMS devices with silicon CMOS electronics, package them in controlled environments, e.g. vacuum for MEMS resonators, and provide industry standard electrical interconnections such as solder bumps. However, to do so requires through-wafer via-based electrical interconnections. However, the fragile nature of the MEMS devices, the requirement for vacuum, hermetic sealing, and the stresses placed on metallization membranes are not present in conventional CMOS packaging. Accordingly there is provided a means of reinforcing through-wafer vias for integrated MEMS-CMOS circuits by in-filling the through-wafer electrical vias with low temperature deposited ceramic materials deposited with processes compatible with post-processing of CMOS electronics. Beneficially ceramics such as silicon carbide provide enhanced mechanical strength, enhanced expansion matching, and increased thermal conductivity in comparison to silicon and solder materials. The ceramic reinforcing may be further adapted to include micro-channels for the provisioning of liquid cooling through the structures.

主权项

1. A method comprising:
providing a semiconductor substrate having first and second surfaces separated by the thickness of the semiconductor substrate, the first surface of the semiconductor substrate being one having or to have an electronic circuit fabricated within or upon; fabricating through the substrate a via, the via comprising at least a first opening in the first surface of the substrate and a second opening in the second surface of the substrate; filling a first predetermined portion of the via with a first electrically conductive material to provide an electrical connection from the first surface to the second surface and to provide an electrical connection to a microelectromechanical systems (MEMS) device; and after filling the first predetermined portion of the via with the first electrically conductive material, filling a second predetermined portion of the via with an electrically non-conductive filler material with a process having a maximum exposure to the substrate during manufacturing of at least one of 250° C., 300° C., and 350° C., the second predetermined portion of the via being the full interior volume of the via from the first surface of the substrate to a first predetermined depth from the second surface of the substrate.