| 发明名称 |
STORAGE DEVICE, MEMORY CELL, AND DATA WRITING METHOD |
| 摘要 |
A memory cell (1) includes a first storage circuit (2) with a write time t1 and a data retention time τ1 and a second storage circuit (3) with a write time t2 and a data retention time τ2 (t1<t2 and τ1<τ2). A row decoder supplies write data to the memory cell (1) via a word line (WL) to write the data on the first storage circuit (2) over a write time tW that is longer than the write time t1 and that is shorter than the write time t2. A PL control circuit (4) supplies power to the memory cell (1) for a time that is longer than the write time t2 when the write data is supplied to the memory cell (1), writes, on the second storage circuit (3), the data written on the first storage circuit (2) once the supply of the write data is stopped, and stops the supply of the power to the memory cell (1) after a lapse of the write time t2 following start of the supply of the write data. |
| 申请公布号 |
US2015332745(A1) |
申请公布日期 |
2015.11.19 |
| 申请号 |
US201314758100 |
申请日期 |
2013.12.25 |
| 申请人 |
TOHOKU UNIVERSITY |
发明人 |
Ohsawa Takashi;Endoh Tetsuo |
| 分类号 |
G11C7/22;G11C11/16;G11C13/00 |
主分类号 |
G11C7/22 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A storage device comprising:
a memory cell comprising a first storage circuit with a write time t1 and a data retention time τ1 and a second storage circuit with a write time t2 and a data retention time τ2 (t1<t2 and τ1<τ2); a power control circuit for controlling power supply to the memory cell; and a write data supply circuit for supplying write data to the memory cell, wherein a data storage node of the first storage circuit and a data storage node of the second storage circuit are connected each other; the write data supply circuit supplies write data to the memory cell to write the data on the first storage circuit over a write time tW that is longer than the write time t1 which is a time necessary for writing data on the first storage circuit and that is shorter than the write time t2 which is a time necessary for writing data on the second storage circuit, and stops the supply of the write data after the elapse of write time tW; and the power control circuit supplies power to the memory cell over a time that is longer than the write time t2 of the second storage circuit when the write data is supplied from the write data supply circuit to the memory cell, writes, on the second storage circuit, the data written on the first storage circuit once the supply of the write data is stopped, and stops the supply of the power to the memory cell after a lapse of the write time t2 of the second storage circuit following start of the supply of the write data. |
| 地址 |
Miyagi JP |
