Area Optimized Driver Layout

摘要

A computerized method for designing a layout of a driver includes analyzing a schematic circuit. PMOSFETs coupled between first common nodes are grouped into one or more first classes. NMOSFETs coupled between second common nodes are grouped into one or more second classes. The method further includes generating the layout for each MOSFET at each location in a layout area of the driver by generating a super parameterized cell (PCELL) layout block comprising a master MOSFET PCELL and a master guard ring PCELL for each of the first class and the second class. The master MOSFET PCELL includes a first set of parameters for the MOSFET and the master guard ring PCELL includes a second set of parameters for the guard ring around the MOSFET. A child PCELL of the master MOSFET PCELL and the master guard ring PCELL are instantiated at each location in the layout area.

主权项

1. A computerized method for designing a layout of a driver, the method comprising:
analyzing a schematic circuit comprising PMOSFETs and NMOSFETs; grouping PMOSFETs coupled between first common nodes into one or more first classes; grouping NMOSFETs coupled between second common nodes into one or more second classes; and generating the layout for each MOSFET at each location in a layout area of the driver by
generating a super parameterized cell (PCELL) layout block comprising a master MOSFET PCELL and a master guard ring PCELL for each of the first class and the second class, the master MOSFET PCELL comprising a first set of parameters for the MOSFET and the master guard ring PCELL comprising a second set of parameters for the guard ring around the MOSFET, wherein the first and the second parameters include all design rules relating to the layout of the driver, andinstantiating a child PCELL of the master MOSFET PCELL and the master guard ring PCELL at each location in the layout area, the child PCELLs inheriting all the first and the second parameters and including layout cell location information.