FRACTIONAL-N PHASE LOCKED LOOP CIRCUIT

摘要

A fractional-N phase locked loop (PLL) circuit (104, 600, 800) is provided. The PLL circuit (104, 600, 800) generates a spread spectrum clock (SSC), using average techniques to suppress phase interpolator nonlinearity. The PLL circuit (600, 800) includes fractional dividers (606, 806) with hybrid finite impulse response (FIR) filtering. Furthermore, a small size and low power divider (606, 806) for a hybrid FIR fractional-N PLL circuit (600, 800) is provided.