SPLIT GATE MEMORY DEVICES AND METHODS OF MANUFACTURING

摘要

Some embodiments of the present disclosure relate to a memory device, which includes a floating gate formed over a channel region of a substrate, and a control gate formed over the floating gate. First and second spacers are formed along sidewalls of the control gate, and extend over outer edges of the floating gate to form a non-uniform overhang, which can induce a wide distribution of erase speeds of the memory device. To improve the erase speed distribution, an etching process is performed on the first and second spacers prior to erase gate formation. The etching process removes the overhang of the first and second spacers at an interface between a bottom region of the first and second spacers and a top region of the floating gate to form a planar surface at the interface, and improves the erase speed distribution of the memory device.

主权项

1. A memory device, comprising:
a semiconductor substrate comprising first and second source/drain regions, which are separated from one another by a channel region; a floating gate arranged over the channel region, wherein the floating gate has an upper surface with a first width and wherein a first dielectric separates the floating gate from the channel region; a control gate arranged over the floating gate, wherein the control gate has a lower surface with a second width that is less than the first width, and wherein a second dielectric separates the control gate from the floating gate; and first and second spacers formed along sidewalls of the control gate and arranged over outer edges of the floating gate upper surface, wherein lower sidewall regions of the first and second spacers taper down towards a neck region within the floating gate, wherein the neck region comprises a third width that is less than the second width of the upper surface.