Apparatus and method for conversion between analog and digital domains with a time stamp for digital control system and ultra low error rate communications channel

摘要

An apparatus and method is disclosed with embodiments of a: 1. digital to analog and reference time converter; 2. analog and reference time to digital converter; 3. Sheahan non-linear time-varying, analog and digital control system; and 4. Sheahan Communication Channel are described in detail herein. Some embodiments use time stamp having 72 bits of time data sufficient to identify each clock pulse of a 9.192631770 GHz clock signal plus an additional 8 bits representing 28=256 interpolated clock phases in order reach a resolution of approximately 0.425 picoseconds per clock phase. Thus an 80 bit time stamp is generated and used as described herein.

主权项

1. A method for communicating digital data, comprising the steps of:
converting the digital data to analog data at an absolute reference time; generating a defined absolute reference time stamp representing the absolute reference time for each bit of converted digital data; transmitting the analog data and the defined absolute reference time stamp; receiving the analog data and the defined absolute reference time stamp; correcting erroneous signals in the analog data with the defined absolute reference time stamp to improve a bit error rate impacted by at least one of multipath distortion, frequency error, phase noise, timing jitter, timing synchronization error and recovered clock phase error; and converting the analog data to digital data.