High-voltage level conversion circuit

摘要

The present disclosure provides a high-voltage level conversion circuit at least comprising a first NMOS transistor, a first PMOS transistor, a second NMOS transistor, a second PMOS transistor, a third PMOS transistor, a third NMOS transistor, a fourth PMOS transistor and a fourth NMOS transistor for receiving an input signal have a first voltage level and a second voltage level and converting the input signal to an output signal having a third voltage level and a fourth voltage level. Compared to conventional high-voltage level conversion circuits the provided high-voltage level conversion circuit occupies less circuit area.

主权项

1. A high-voltage level conversion circuit comprising:
a first NMOS transistor, the gate of the first NMOS transistor connected to an input terminal for receiving an input signal, the source of the first NMOS transistor connected to a first voltage level, wherein the input signal comprises the first voltage level and a second voltage level; a first PMOS transistor, the gate of the first PMOS transistor connected to the input terminal for receiving the input signal, the source of the first PMOS transistor connected to the second voltage level; a second NMOS transistor, the drain of the second NMOS transistor connected to the drain of the first PMOS transistor, the gate and the drain of the second NMOS transistor connected together, thus the voltage across the second NMOS transistor being at least a threshold voltage when the second NMOS transistor is conducted; a second PMOS transistor, the drain of the second PMOS transistor connected to the drain of the first NMOS transistor, the gate and the drain of the second PMOS transistor connected together, thus the voltage across the second PMOS transistor being at least a threshold voltage when the second PMOS transistor is conducted; a third PMOS transistor, the drain of the third PMOS transistor connected to the source of the second PMOS transistor, the source of the third PMOS transistor connected to a third voltage level; a third NMOS transistor, the drain of the third NMOS transistor connected the source of the second NMOS transistor, the source of the third NMOS transistor connected to a fourth voltage level; a fourth PMOS transistor, the gate of the fourth PMOS transistor connected to the drain of the first NMOS transistor, the source of the fourth PMOS transistor receiving the third voltage level, the drain of the fourth PMOS transistor connected to the gate of the third NMOS transistor; and a fourth NMOS transistor, the gate of the fourth NMOS transistor connected to the drain of the first PMOS transistor, the source of the fourth NMOS transistor receiving the fourth voltage level, the drain of the fourth NMOS transistor connected to the gate of the third PMOS transistor; wherein the drain of the fourth PMOS transistor and the drain of the fourth NMOS transistor are for generating a high-voltage level conversion signal.