Reception circuit and semiconductor integrated circuit

摘要

A burst mode CDR detects an edge from a data signal superimposed with a clock, and generates a recovered clock by means of a voltage controlled oscillator whose oscillation operation is reset based on a timing when the edge is detected. A phase adjustment unit adjusts the phase of a data signal so as to coincide with the phase of a recovered clock. A PLL-based CDR adjusts the oscillation frequency of the recovered clock by means of the voltage controlled oscillator, based on a phase difference between a data signal whose phase has been adjusted by the phase adjustment unit and a feedback clock from the voltage controlled oscillator. A determination unit determines the value of the data signal at a timing when the signal level of the recovered clock transitions.

主权项

1. A reception circuit comprising:
a first clock recovery circuit that detects an edge from a data signal superimposed with a clock and generates a recovered clock by means of a voltage controlled oscillator whose oscillation operation is reset based on a timing when the edge is detected; a phase adjustment circuit that adjusts a phase of the data signal so as to coincide with a phase of the recovered clock; a second clock recovery circuit that, based on a phase difference between the data signal whose phase has been adjusted by the phase adjustment circuit and a feedback clock from the voltage controlled oscillator, adjusts an oscillation frequency of the recovered clock by means of the voltage controlled oscillator; and a determination circuit that determines a value of the data signal, whose phase has been adjusted by the phase adjustment circuit, at a timing when a signal level of the recovered clock transitions; wherein the phase adjustment circuit adjusts the phase of the data signal by delaying the data signal based on a delay amount in the first clock recovery circuit.