Semiconductor device, portable communication terminal, IC card, and microcomputer

摘要

The present invention provides a noncontact interface technique capable of performing communication operation without stopping an internal operation even when a clock signal cannot be extracted from a carrier wave. In a semiconductor device that receives a modulated carrier wave from an antenna, generates an internal clock signal on the basis of a clock signal extracted from the received carrier wave, and performs operation synchronously with the internal clock signal, a PLL circuit that receives the extracted clock signal and generates the internal clock signal is provided with a voltage control oscillation function. In the case where the clock signal extracted from the carrier wave is discretely interrupted, the function makes the internal clock signal maintained at a frequency immediately before the interruption. With the configuration, even when the clock signal extracted from the carrier wave is interrupted, internal data processes such as decoding and bus interfacing can be continued.

主权项

1. A semiconductor device comprising:
a reception circuit configured to receive an amplitude-modulated carrier wave from an antenna, to demodulate said carrier wave, and to extract a clock signal from the carrier wave; a logic circuit configured to perform a data process on a reception signal by the reception circuit; and a PLL circuit configured to receive the clock signal extracted by the reception circuit, to generate an internal clock signal of the logic circuit, and to control synchronization of the internal clock signal with the extracted clock signal, wherein the PLL circuit is further configured to continue to generate the internal clock signal during a period of stopping of a change in the extracted clock signal, wherein the PLL circuit comprises an error current generation circuit coupled to a low pass filter, and a voltage controlled oscillation circuit coupled to an output of the low pass filter, wherein the error current generation circuit outputs an error current signal to the low pass filter which is based on a charge error signal and a discharge error signal, wherein the error current generation circuit is configured to output said error current signal to cause the low pass filter to stop charging/discharging during the period of stopping of a change in the extracted clock signal and wherein the PLL circuit comprises
a phase frequency difference detection circuit configured to generate a charge error signal and a discharge error signal in accordance with a phase difference between the extracted clock signal and a feedback signal synchronized with an internal clock signal; anda charge/discharge circuit configured to charge an output node upon receiving the charge error signal and to discharge the output node upon receiving the discharge error signal,wherein the output node of the charge/discharge circuit is coupled to an input of the low pass filter, andwherein the phase frequency difference detection circuit is configured to:when a frequency of the extracted clock signal and a frequency of the feedback signal are equal to each other, and a phase of the feedback signal follows a phase of the extracted clock signal by 90 degrees, the phase frequency difference detection circuit equalizes a charge amount of the output node by the charge error signal and a discharge amount of the output node by the discharge error signal, andwhen the frequency of the extracted clock signal and the frequency of the feedback signal are not equal to each other, or the phase of the feedback signal does not follow the phase of the extracted clock signal by 90 degrees, the phase frequency difference detection circuit shifts the charge amount or the discharge amount of the output node so as to suppress a deviation amount, and the phase frequency difference detection circuit stops both charging of the output node being performed in response to the charge error signal and discharging of the output node being performed in response to the discharge error signal in accordance with disappearance of the first period caused by stop of a change in the extracted clock signal.