发明名称 |
At-Speed Test of Memory Arrays Using Scan |
摘要 |
A method and apparatus for conducting at-speed testing of a memory array in an integrated circuit (IC) is disclosed. In one embodiment, an IC includes a memory array and a plurality of input circuits coupled to provide input signals into the memory array. Each of the plurality of input circuits includes an input flip-flop having a data output coupled to a corresponding input of the memory array, selection circuitry configured to select a data path to a data input of the input flip-flop and a data path shift register coupled to control a state of a selection signal provided to the selection circuitry, wherein the data path shift register includes a plurality of multiplexers. When operating the IC in a test mode, the plurality of input circuits is configured to provide input signals into the memory array at an operational clock speed of the IC. |
申请公布号 |
US2015325314(A1) |
申请公布日期 |
2015.11.12 |
申请号 |
US201414273851 |
申请日期 |
2014.05.09 |
申请人 |
Oracle International Corporation |
发明人 |
Ziaja Thomas A;Gala Murali M. R. |
分类号 |
G11C29/12;G11C7/10 |
主分类号 |
G11C29/12 |
代理机构 |
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代理人 |
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主权项 |
1. An integrated circuit (IC) comprising:
a memory array; a plurality of input circuits coupled to provide input signals into the memory array, wherein each of the plurality of input circuits includes:
an input flip-flop having a data output coupled to a corresponding input of the memory array;selection circuitry configured to select a data path to a data input of the input flip-flop; anda data path shift register coupled to control a state of a selection signal provided to the selection circuitry, wherein the data path shift register includes a plurality of multiplexers; and wherein, when operating in a test mode, the plurality of input circuits is configured to provide input signals into the memory array at an operational clock speed of the IC. |
地址 |
Redwood City CA US |