Method, Device, and System for Processing PCIe Link Fault

摘要

In a Peripheral Component Interconnect Express (PCIe) system, a first PCIe apparatus determines that at least one of lanes of a link between the first PCIe apparatus and a second PCIe apparatus is disabled, wherein the link includes M lanes numbered in a first order. Based upon the determination, the first PCIe apparatus obtains a number N indicating a number of available lanes of the link by performing a lane negotiation with the second PCIe apparatus. Then, a processor determines that N

主权项

1. A method performed by a Peripheral Component Interconnect Express (PCIe) system which includes a processor and a first PCIe apparatus, the method comprising:
determining, by the first PCIe apparatus, that at least one of lanes of a link between the first PCIe apparatus and a second PCIe apparatus is disabled, wherein the link includes M lanes numbered in a first order; reporting, by the first PCIe apparatus and to the processor, a device identifier (ID) of the first PCIe apparatus based on the determination that the at least one of the lanes of the link between the first PCIe apparatus and the second PCIe apparatus is disabled; obtaining, by the first PCIe apparatus, a number N indicating a number of available lanes of the link by performing a lane negotiation with the second PCIe apparatus; obtaining, by the processor, the number N and a number M indicating a total number of lanes of the link from the first PCIe apparatus according to the device ID; determining, by the processor, that N