发明名称 3D CHIP-ON-WAFER-ON-SUBSTRATE STRUCTURE WITH VIA LAST PROCESS
摘要 Disclosed herein is a package comprising a first redistribution layer (RDL) disposed on a first side of a first semiconductor substrate and a second RDL disposed on a second semiconductor substrate, wherein the first RDL is bonded to the second RDL. First conductive elements are disposed in the first RDL and the second RDL. First vias extend from one or more of the first conductive elements through the first semiconductor substrate to a second side of the first semiconductor substrate opposite the first side. First spacers are interposed between the first semiconductor substrate and the first vias and each extend from a respective one of the first conductive elements through the first semiconductor substrate.
申请公布号 US2015325520(A1) 申请公布日期 2015.11.12
申请号 US201414444681 申请日期 2014.07.28
申请人 Taiwan Semiconductor Manufacturing Company, Ltd. 发明人 Yu Chen-Hua;Chen Ming-Fa;Tsai Wen-Ching;Yeh Sung-Feng
分类号 H01L23/538;H01L21/768;H01L23/00 主分类号 H01L23/538
代理机构 代理人
主权项 1. A package comprising: a first redistribution layer (RDL) disposed on a first side of a first semiconductor substrate; a second RDL disposed on a second semiconductor substrate, wherein the first RDL is bonded to the second RDL; first conductive elements disposed in the first RDL and the second RDL; first vias extending from one or more of the first conductive elements through the first semiconductor substrate to a second side of the first semiconductor substrate opposite the first side; and first spacers interposed between the first semiconductor substrate and the first vias and each extending from a respective one of the first conductive elements through the first semiconductor substrate.
地址 Hsin-Chu TW