| 摘要 |
A computer implemented system and method of identification of useful untested states of an electronic design, comprising, parsing at least one netlist of a representation of the electronic design comprised at least in part of at least one analog portion, determining at least one instrumentation point based on the at least one netlist, generating at least one instrumented netlist based on the at least one instrumentation point and determining an analog verification coverage utilizing the at least one instrumented netlist. |
