发明名称 制御装置、解析装置、解析方法、および解析プログラム
摘要 <p>A cache controller receives a reference request from a CPU executing a program in which information indicative of a reference request specifying in shared memory, an area not having an update request and information indicative of a snoop reference request are distinguished from one another. When the reference request specifying an area not having the update request is received, the cache controller acquires from the shared memory and without performing a snoop process, information stored in the specified area. The cache controller stores the information acquired from the shared memory to the cache memory of the CPU executing the program.</p>
申请公布号 JP5811194(B2) 申请公布日期 2015.11.11
申请号 JP20130556102 申请日期 2012.01.30
申请人 发明人
分类号 G06F12/08;G06F15/167 主分类号 G06F12/08
代理机构 代理人
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