| 摘要 |
<p>At the time of write leveling, in order to avoid an initialization time from becoming long, the write leveling control unit (250) firstly adjusts a delay amount of a DQS control unit (242) and a DQ control unit (244) in a range of less than one clock cycle. Next, for each of SDRAMs (282), the write leveling control unit (250) compares a read data sequence, which is obtained by writing an expected value sequence and reading the read data sequence, with an expected value data sequence and adjusts the delay amount of the DQS control unit (242) and the DQ control unit (244) by a unit of a clock cycle according to a result of the comparison. At the time of the above-mentioned writing, control is performed so that the DQS control unit (242) outputs a data strobe signal (DQS) that is longer than a burst length, which is defined in the standard, by "2*M" (M: an integer of one or greater) clock cycle, and the DQ control unit (244) adds M pieces of data to a beginning and end of the expected value data sequence, in which the number of data in the expected value data sequence matches the above-mentioned burst length, and outputs the expected value data sequence with the added data.</p> |
